Pipelined processing often provides improved performance due to the ability to process multiple instructions at various components of a pipeline simultaneously. Performance further may be enhanced using branch prediction techniques whereby a branch prediction unit of a processing device predicts whether a branch presented by an upcoming change of flow (COF) instruction is taken. If the branch is predicted to be taken, the instructions following the branch may be preloaded into the instruction cache of the processing device, and also may be executed in whole or in part before the COF instruction is resolved. However, in the event of a misprediction, the pipeline typically is flushed and any results of the execution of the instructions associated with the misprediction are discarded. Thus, misprediction often results in considerable power consumption by the processor as well as wasted processing cycles.
Regardless of the effectiveness of a processor's branch prediction, it will be appreciated that the fetching and execution of instructions by the pipelined processing device may not involve or require the use of one or more components of the processing device. To illustrate, the execution of an instruction representing an integer operation typically does not require the use of a floating point unit (FPU) of the processing device. The processing device therefore often unnecessarily consumes power while maintaining certain components in an enabled status even though an  upcoming instruction stream does not require the use of the certain components. Accordingly, a system and method to reduce the power consumption of a processing device and reduce the penalty associated with mispredicted branches would be advantageous.